Design and Analysis of Pipelined Discrete Wavelet Transform Architectures

Abstract

This paper investigates the trade-offs between area, power and throughput (clock cycles) of several implementations of the discrete wavelet transform (DWT) using direct form in various sampling rates and pipelined architectures. The results of four different architectures synthesized, simulated and emulated on FPGA (Xilinx-XC2V6000). It is shown that the pipelined architectures provide the best area, power consumption, and throughput trade-offs under sampling rate, hardware utilization, and hardware. These high-efficiency architectures are comprised of a transform module, an address sequencer, and a RAM module. The transform modules have uniform and regular structure, simple control flow, and local communication. According to the architecture with 2-samples per clock cycle, the power consumption of the architectures with 4- and 8-samples per clock cycle reduce power by 33%, but the hardware requirements are increased by 33%, 167% and 400%, respectively. The throughputs of the architectures with 4-, 8- and 16-samples per clock cycle are improved by 100%, 300%, 700%, respectively. These four proposed architectures are very suitable for VLSI implementation of new-generation image compression systems, such as JPEG-2000.