Low Power Mapping and Pipelined Scheduling Using Tabu Search

Abstract

An tabu search based approach for distributed embedded systems synthesis is presented in this paper. This approach maps each computation task of a particular application onto a system component with multiple supply voltages, schedules the execution of these computation tasks and communication time of global shared bus into pipeline stages. The objective is to minimize the total power consumption subject to the throughput constraint on the pipelined system architecture. The results of experiments show a very good performance to obtain the near-optimal solution compared with global optimal solution obtained by ILP(Integer Linear Programming) approach [1] and analysis the number of orderings in ordering pool to trade-off speed and quality of solution.