完整後設資料紀錄
DC 欄位 | 值 | 語言 |
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dc.contributor.author | Wu, Kun-Yi | |
dc.contributor.author | Kuang, Shiann-Rong | |
dc.date.accessioned | 2009-06-02T07:05:42Z | |
dc.date.accessioned | 2020-05-25T06:48:48Z | - |
dc.date.available | 2009-06-02T07:05:42Z | |
dc.date.available | 2020-05-25T06:48:48Z | - |
dc.date.issued | 2009-02-10T02:01:38Z | |
dc.date.submitted | 2009-01-19 | |
dc.identifier.uri | http://dspace.lib.fcu.edu.tw/handle/2377/11125 | - |
dc.description.abstract | In this paper, we present instruction scheduling and register relabeling algorithms for ARM processor to reduce switching activity between instructions. Given the original assembly code and machine code produced by compiler, the proposed algorithm first builds the corresponding DAG (Directed Acyclic Graph) and DDG (Data Dependence Graph) of the assembly code. Then we reorder the sequence of instructions in DAG by our proposed list scheduling algorithm (move_ahead) and re-allocate registers into variables of DDG by tabu search to decrease the switching activity. Experimental results show that our proposed algorithms can achieve 5 % to 25% decrement in switching activity without sacrificing any program performance. | |
dc.description.sponsorship | 淡江大學,台北縣 | |
dc.format.extent | 6p. | |
dc.relation.ispartofseries | 2008 ICS會議 | |
dc.subject | Instruction scheduling | |
dc.subject | register relabeling | |
dc.subject | tabu search | |
dc.subject | switching activity | |
dc.subject.other | Computer Architecture | |
dc.title | Instruction Scheduling and Register Relabeling Algorithms for Reducing Switching Activity between Instructions | |
分類: | 2008年 ICS 國際計算機會議 |
文件中的檔案:
檔案 | 描述 | 大小 | 格式 | |
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ce07ics002008000047.pdf | 115.62 kB | Adobe PDF | 檢視/開啟 |
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