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dc.contributor.authorTseng, Chia-Ying
dc.contributor.authorChen, Yen-Chih
dc.date.accessioned2009-06-02T07:05:55Z
dc.date.accessioned2020-05-25T06:49:02Z-
dc.date.available2009-06-02T07:05:55Z
dc.date.available2020-05-25T06:49:02Z-
dc.date.issued2009-02-12T07:21:48Z
dc.date.submitted2009-02-12
dc.identifier.urihttp://dspace.lib.fcu.edu.tw/handle/2377/11235-
dc.description.abstractWith the growing of multimedia codec types, the huge amount of produced computing can not be handled by a single processor now. Therefore, we hope that the programs which include many computations can be processed by multiprocessors. In addition, the core operated in embedded system platform also gradually becomes multiprocessor from a single processor. In this paper, we design a four-processor system using NiosII soft-core and implement our MPSoC architecture (includes 4K I-cache, 1MB SRAM, 32MB SDRAM, 16MB Flash) and design the executable programs running in multiprocessor via hardwire Mutex element. We use the hardwire Mutex core to access the shared memory in the program. The implemented result shows that the quad-core system architecture that we proposed can execute the program concurrently at the same time.
dc.description.sponsorship淡江大學,台北縣
dc.format.extent6p.
dc.relation.ispartofseries2008 ICS會議
dc.subjectFPGA
dc.subjectNios II
dc.subjectMPSoC
dc.subjectSoft-core
dc.subjectMulti-core
dc.subject.otherArchitecture and Applications for Multi-Core Processors
dc.titleDesign and Implementation of Multiprocessor System on a Chip (MPSoC) Based on FPGA
分類:2008年 ICS 國際計算機會議

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