完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.author | Wang, Chua-Chin | |
| dc.contributor.author | Hsueh, Ya-Hsin | |
| dc.contributor.author | Kuo, Ting-Wan | |
| dc.contributor.author | Hu, Ron | |
| dc.date.accessioned | 2009-08-23T04:41:30Z | |
| dc.date.accessioned | 2020-05-25T06:39:03Z | - |
| dc.date.available | 2009-08-23T04:41:30Z | |
| dc.date.available | 2020-05-25T06:39:03Z | - |
| dc.date.issued | 2006-10-16T01:34:54Z | |
| dc.date.submitted | 2002-12-18 | |
| dc.identifier.uri | http://dspace.lib.fcu.edu.tw/handle/2377/1296 | - |
| dc.description.abstract | A novel voltage tripler using 4 clocks with different phases is presented in this work. Both the positive and negative polarities of voltage are generated to serve as the boosted voltage and back bias voltage. The proposed design is carried out by pass transistors and switched capacitors. The largest generated voltage which the proposed design can provide is +11.09 V and -10.62 V given VOD = 3.3 V when the circuit is implemented by TSMC 0.35 u 1P4M CMOS technology. | |
| dc.description.sponsorship | 東華大學,花蓮縣 | |
| dc.format.extent | 14p. | |
| dc.format.extent | 627220 bytes | |
| dc.format.mimetype | application/pdf | |
| dc.language.iso | zh_TW | |
| dc.relation.ispartofseries | 2002 ICS會議 | |
| dc.subject | BVG | |
| dc.subject | memory devices | |
| dc.subject | BBG | |
| dc.subject | programming voltage | |
| dc.subject | boosted voltage generator | |
| dc.subject | back bias generator | |
| dc.subject.other | Computer Systems | |
| dc.title | A Boosted Wordline Voltage Generator for Embedded Low-Voltage Memories | |
| 分類: | 2002年 ICS 國際計算機會議 | |
文件中的檔案：
| 檔案 | 描述 | 大小 | 格式 | |
|---|---|---|---|---|
| ce07ics002002000031.PDF | 612.52 kB | Adobe PDF | 檢視/開啟 |
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