The Design of Math Core in CPLD for the AES Application

Abstract

In contemporary communication system design, the SoC integrates more and more IPs to perform the functions such as error correction code and cryptography. In cryptography, the AES needs much more powerful math modules with high flexibility and operational diversity to cope with the attack from outside [1]. The CPLD/FPGA is usually chosen for the purposes of simple circuit implement, functional design and testing, IP proof and system integration. The advantages of CPLD/FPGA are high efficiency, flexibility and reconfiguration. In the future, more applications will be developed on CPLD/FPGA instead of VLSI. As AES application needs more flexible transformations to design for diversity, the implementation of math IPs in finite field into programmable devices is very important. Without increasing the complexity of IPs, we propose a modified architecture of math modules for CPLD to increase the overall efficiency and keep high-speed performance [2-7]. In those modules, a multiplicative inverse is specially designed for the application on the fast and flexible system.