A Novel TLB Architecture to Reduce the Miss Rate in Context Switching

Abstract

It is widely known that the Translation Lookaside Buffer (TLB) plays an important role in the address translation mechanism from virtual addresses to physical addresses. If any misses occur, the performance of the processor will seriously degrade. In order to reduce such misses, some methodologies are proposed. Some designs try to improve the associativity or sizes to reduce the conflict or capacity misses, while others try to use superpages to cover more memory spaces. Furthermore, some papers even propose methods to dynamically merging several smaller pages into superpages during the processor execution. These methodologies, especially superpages, can effectively reduce lots of misses for most applications. However, to support the multiprogramming characteristic in all modern OS, the context switching mechanism is needed and the context switching will cause the flush operations for all TLB entries. It will impact on the performance very seriously, especially on today’s high performance processors. However, it’s hard to find an easy implement solution to reduce the misses in context switching. This paper shows what would happen if the page sizes are increased from 4KB to 1MB to explain why larger page size are selected. The paper also presents a novel and easy implemented TLB architecture to reduce the misses in context switching. All simulations were done with modified SimpleScalar 3.0d tool suite and SPEC95 benchmarks. The results show that our methodology can be very useful for multiprogramming environment under specific conditions.