A New Scheme to Reducing Data Stall with Data Prefectching Table and History Table

Abstract

Large scale programs have been developed that has more frequent data access from memory, thus insurring data hazard and data access latency. This often degrades CPU performance, and more seriously, the system may stall. This paper proposes a new scheme to solve the data dependence and to avoid the data hazard. Two tables are added into the DLX pipeline architecture: once is Data Prefetching Table (DPT),and the other is History Table(HT). The HT is used to process the instruction recognition for data dependency detection. If data dependency occurs, the system will immediately send a "reusing" signal to DPT,notiching DPT to deliver the deeded data to ALU. This eliminates the data access latency and expedites CPU. Based on this the Data Prefetching Processor(DPP), i.e.,the pipeline CPU with DPT and HT, is modeled and simulated using the SES/workbench object-oriented graphical modeling and simulation software. Performance comparison between the enhanced structure and traditional pipeline architecture is done to verify the suitability of our proposed scheme.