完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Shu, Wen-Lung | |
dc.date.accessioned | 2009-08-23T04:47:48Z | |
dc.date.accessioned | 2020-05-29T06:17:28Z | - |
dc.date.available | 2009-08-23T04:47:48Z | |
dc.date.available | 2020-05-29T06:17:28Z | - |
dc.date.issued | 2006-10-18T10:55:55Z | |
dc.date.submitted | 2001-12-20 | |
dc.identifier.uri | http://dspace.fcu.edu.tw/handle/2377/1944 | - |
dc.description.abstract | A new hardware sorter which combines both Batcher's parallel merge sort [1] and Stodd's pipelined two way merge sort algorithm [2] is proposed in the paper. This hardware contains one k-sorter and ㏒(n/k) k-to-k mergers, and can sort n records in Ο(n/k) assuming data is retrieved through k parallel data paths. The internal processing algorithm and control unit of this pipelined parallel device have been completely designed. This sorter is readily suitable for VLSI Implementation, and can be used to process very large databases efficiently. | |
dc.description.sponsorship | 中國文化大學,台北市 | |
dc.format.extent | 8p. | |
dc.format.extent | 150684 bytes | |
dc.format.mimetype | application/pdf | |
dc.language.iso | zh_TW | |
dc.relation.ispartofseries | 2001 NCS會議 | |
dc.subject | hardware sorter | |
dc.subject | parallel | |
dc.subject | pipeline | |
dc.subject.other | VLSI system design | |
dc.title | A Pipelined Parallel Hardware Sorter | |
分類: | 2001年 NCS 全國計算機會議 |
文件中的檔案:
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ce07ncs002001000052.pdf | 147.15 kB | Adobe PDF | 檢視/開啟 |
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