Robust Reference Clock Generator Design for DDR Synchronous Devices

Abstract

The rapidly improved performance of latest CPUs introduces higher clock rates for peripheral devices. Moreover, DDR(double data rate)has been one of the most important methods to increase the throughput of a system, e.g., SDRAM. The edges of the reference clock, thus, become deadly important to these high-speed and high-clock applications. In this paper, we present a pulse generator circuit to generate pulses corresponding to the rise edge and fall edge of a given clock, respectively, without any phase shift and delay. These pulse trains can be used to synchronize the peripherals. The noise rejection is also proved when the given clock is coupled with a 10\% noise. The proposed circuit can be applied to other clock rates beyond 133 MHz as long as the sizes of the delay elements are properly tuned.