Architecture Optimization of Broadband Fast Packet Switches with Clustering and Speedup Constraints

Abstract

In this paper, we study how clustering and speedup at the input and output ports of a generic nonblocking packet switch affect switch throughput and port buffer size. By determining the maximum allowable clustering and speedup, an optimal switch configuration can be established for a given VLSI technology. Our performance analysis shows that output port speedup is most effective in increasing through put but has no effect on buffer reduction, while input speedup has a moderate effect on both increasing throughput and decreasing buffer size. Input-port grouping is useful on buffer reduction but has no effect on throughput, while output-port grouping has a moderate effect on increasing throughput and a negligible effect on buffer reduction.