FPGA-Based Reconfigurable Architectures for Neural Network

Abstract

This paper describes the use of FPGA-based reconfigurable architectures to implement artificial neural networks. The research is focused on investigating the properties of FPGAs (Field programmable gate arrays) to determine whether they are suitable hardware solutions, and to experiment with their reconfigurability as potential implementation approaches for neural network computing. Two implementation approaches were proposed. The first proposal, known as the template-based approach, is aimed at producing a computing architecture that combines high computational power with userprogrammable flexibility to handle a wide variety of neural networks. The second approach introduced a partial-RTR (run-time reconfiguration) methodology that formats the native reconfigurable logic resources of an FPGA, allowing its reconfigurable region to be manipulated like a functional entity. The architecture is able to benefit from higher functional density without the complexities associated with conventional partial- RTR methodologies. A prototype system, FRANN, was constructed to test the proposed implementation approaches, and to act as an experimental testbed for future development.