The Fetch Mechanism Issue of X86 Superscalar Processor with Fetch Rules

Abstract

Fetching multiple instructions is the most important job of the superscalar fetcher. However, in x86 Superscalar processors, the variable-length instructions and the complex addressing system make fetching multiple instructions in a cycle difficult. The formats of the x86 instruction are issued in the complexity for parallel fetch of multiple instructions. The model of multiple x86 instruction fetch (MIFM86) is defined with the fetch rules instead of issue rules. By this model, the performances of current x86 processors, affected by each fetch methods, are analyzed and are compared.