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dc.contributor.authorWu, Ho-Ting
dc.date.accessioned2009-08-23T04:39:29Z
dc.date.accessioned2020-05-25T06:26:00Z-
dc.date.available2009-08-23T04:39:29Z
dc.date.available2020-05-25T06:26:00Z-
dc.date.issued2006-10-27T07:16:43Z
dc.date.submitted1996-12-19
dc.identifier.urihttp://dspace.lib.fcu.edu.tw/handle/2377/2722-
dc.description.abstractWe propose an integrated algorithm to jointly support the transmission of synchronous and asynchronous traffic across a full-duplex ATM ring network which employs a destination removal procedure. This algorithm is an extension of the FECCA algorithm introduced in [1]. A framed approach is employed. Each frame consists of a “synchronous subframe” followed by an “asynchronous subframe”. Each node can prescribe a synchronous quota in each frame, specifying the maximum number of synchronous connections it wishes to support per frame. The reverse ring is used for the transmission of signaling information. As a result, the integrated scheme enables the occasional transmission of asynchronous data within the synchronous subframe and permits extra cell transmission beyond specified quotas. Thus, this integrated scheme provides guaranteed bandwidth for the support of a quota of synchronous connections while at the same time is able to efficiently (and in a fair manner) utilize the remaining bandwidth to support asynchronous traffic. Illustrative performance examples are shown to demonstrate the effectiveness and efficiency of this integrated algorithm.
dc.description.sponsorship中山大學,高雄市
dc.format.extent8p.
dc.format.extent712395 bytes
dc.format.mimetypeapplication/pdf
dc.language.isozh_TW
dc.relation.ispartofseries1996 ICS會議
dc.subject.otherATM
dc.titleA Fair and Efficient Integrated Protocol for a Full-Duplex ATM Ring Network
分類:1996年 ICS 國際計算機會議

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