A New Bus Allocation Algorithm for Interconnection Networks of Multiprocessor Systems

Abstract

In shared multiprocessor systems, the interconnection network is usually the bottleneck of system performance. Memory references usually have two kinds of locality: temporal locality and spatial locality. If a processor references a memory module, it tends to reference the same memory module again. If we do not release a bus that connects the processor and the memory module immediately, we can use the same bus directly without reconfiguration when the processor references the same memory module again. Thus, we propose a new bus allocation algorithm for interconnection networks of multiprocessor system. A pipelined one-sided crossbar switch, which is essentially a multiple bus, is used to illustrate our design approach. Experimental results show that the new algorithm uses buses more efficiently and reduces the number of reconfigurations. The performance (throughput)using the new bus allocation algorithm is up to 3 times higher than that using the original algorithm. The contribution of this work is designing a high throughput interconnection network to match high performance multiprocessors and to eliminate the performance bottleneck.