An Improved Dispatch and Issue Mechanis with Dynamic Instruction Reuse

Abstract

Among researches about improving performance on superscalar processor, an idea is emerged and it is named dynamic instruction reuse. This concept will help improving the performance and the utilization of the resource, which can be reduced at the same time. In this paper we propose an improved dispatch and issue mechanism with dynamic reuse in superscalar. The percentage of average reduction of total number of cycles is from 12.5% to 15.2% by using dynamic instruction reuse and trivial computation.