A Method of Improving Translating Performance in the CISC/RISC Hybrids

Abstract

This paper proposes a method to improve the translating performance in the CISC/RISC hybrid processors. This method introduces the design of a new decoder architecture which contains an instruction scheduler and a new translator type with a combination of one simple, one general and one complex translators (1S+1G+1C). To improve the translating performance is to increase the number of CISC instructions translated per cycle, which is the goal of this paper. We build a decoder architecture model for the proposed method to measure its translating performance. Besides, two different decoder architecture models are built for comparison. These three models are used to evaluate the effect of the different design issues for the translating performance. These issues include instruction mix, instruction dependencies, translator type, scheduler, and search window size. The evaluation results show that the model for the new decoder architecture with 1S+1G+1C translators and a scheduler performs better than other models. In addition, the results also show that the new decoder architecture has the ability to translate more instructions every cycle than other current CISC/RISC hybrid microprocessors do in average.