The Design And Implementation of An Object-Oriented Trace-Driven Simulator for Superscalar CISC Processors

Abstract

Developing a superscalar complex-instruction-set-computing (CISC) processor requires trade-off of various design alternatives. In this paper, we present a trace-driven simulator to help us deal with that difficult, iterative task. The simulator was written in C++ and well-structured so that it can be easily reconfigured for evaluating various design trade-offs. The reconfigurable parts include numbers of pipeline stages and functional units, sizes of internal queues and buffers, latencies of each functional unit, and various scheduling and control schemes. We demonstrate its flexibility and versatility by simulating four DOS benchmark programs and reporting their results.