Evaluation on Memory Buffers for Shared Bus Multiprocessors

Abstract

This paper evaluates the optimal number of memory buffers we should include in the memory controller to improve the system performance. We focus on shared-bus multiprocessor (MP) systems adopting DRAM ( Dynamic Random Access Memory ) as the shared memory. In order to evaluate the design tradeoff in various conditions, extensive simulation was conducted by employing a commercial simulation tool. Using the MP system model constructed in simulation tool, we could evaluate the optimal number of read or write buffers in the memory controllers under different configurations. In addition, it could even combine the model with trace-file under a slight modification. By adding optimal number of read and write buffers, the system performance is shown to increase efficiently and significantly.