Hardware-Efficient Systolic Array Implementations of Euclid's Algorithm for Inversion and Division in GF(2m)

Abstract

In this paper, four parallel-in parallel-out systolic arrays are proposed for computing inversion or division in finite fields GF(2m) based on new variants of Euclid’s algorithm with the standard basis representation. Two of these arrays involve O(m2) area-complexity and O(1) time-complexity. The other two involve O(m) area-complexity and O(m) time-complexity. They are highly regular, modular, and thus well suited to VLSI implementation. As compared to existing related systolic architectures：1) the former two and the one in [14] have the same area and time complexities, but our proposed arrays involve less hardware area； 2) the latter two with O (m) area-complexity gains a significant improvement in area complexity.