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dc.contributor.authorChang, Chi-Fu
dc.contributor.authorHsu, Yarsun
dc.date.accessioned2011-01-19T04:17:40Z
dc.date.accessioned2020-05-18T03:10:59Z-
dc.date.available2011-01-19T04:17:40Z
dc.date.available2020-05-18T03:10:59Z-
dc.date.issued2011-01-19T04:17:40Z
dc.date.submitted2010-01-10
dc.identifier.urihttp://dspace.lib.fcu.edu.tw/handle/2377/29912-
dc.description.abstractThe design of a NoC simulator can significantly affect its ability to explore various design space and simulation accuracy. It’s not easy to achieve both wide-range design space exploration and detailed characterization of hardware components simultaneously. This paper presents a kind of NoC modeling in an object oriented flavor: object oriented NoC modeling (“OONoC” in brief). OONoC divides the NoC design space into many design blocks and each block into many abstraction levels. OONoC can extend the exploration space of NoC, study hardware characteristics, and significantly reduce the coding effort of a new NoC design.
dc.description.sponsorshipNational Cheng Kung University,Tainan
dc.format.extent10p.
dc.relation.ispartofseries2010 ICS會議
dc.subjectNetwork-on-chip
dc.subjectNoC
dc.subjectDesign space
dc.subject.otherComputer Architecture, SoC, and Embedded Systems
dc.titleObject Oriented Network-On-Chip Modeling
分類:2010年 ICS 國際計算機會議(如需查看全文,請連結至IEEE Xplore網站)

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