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dc.contributor.authorWang, Sheng-De
dc.contributor.authorChen, Chun-Wei
dc.contributor.authorPan, Michael
dc.contributor.authorHsu, Chih-Hao
dc.date.accessioned2011-01-19T04:19:00Z
dc.date.accessioned2020-05-18T03:11:01Z-
dc.date.available2011-01-19T04:19:00Z
dc.date.available2020-05-18T03:11:01Z-
dc.date.issued2011-01-19T04:19:00Z
dc.date.submitted2011-01-10
dc.identifier.urihttp://dspace.lib.fcu.edu.tw/handle/2377/29922-
dc.description.abstractXML (Extensible Markup Language) is a general language for representation of arbitrary data structures. It has been widely used in Internet applications and in computer systems because of the extension and user customization features. In order to parse XML documents efficiently, much research has been done to accelerate the processing of XML documents or messages. The hardware-accelerated approach is becoming important due to a higher performance is getting expected. Current hardware platforms for processing XML documents lack the capability of checking the syntactic structures for XML documents because of complication. To improve existing design methods, lower the CPU load, and process XML efficiently, we present a hardware accelerated XML parser with well-form checker by using the abstract classification table. The approach provides a testing and verification platform for XML processing. Abstract classification table is an emerging indexing technique to represent the hierarchical structure of XML documents and can accelerate XML processing. In our platform, the hardware accelerator can parse XML documents at 206 Mbps and provide a Giga bit level throughput.
dc.description.sponsorshipNational Cheng Kung University,Tainan
dc.format.extent7p.
dc.relation.ispartofseries2010 ICS會議
dc.subjectXML
dc.subjectACT
dc.subjectVTD
dc.subjectUTF-8
dc.subject.otherComputer Architecture, SoC, and Embedded Systems
dc.titleHardware Accelerated XML Parsers with Well Form Checkers and Abstract Classification Tables
分類:2010年 ICS 國際計算機會議(如需查看全文,請連結至IEEE Xplore網站)

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