完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Chang, Cheng-Ho Jr | |
dc.contributor.author | Lee, Lung-Jen Jr | |
dc.contributor.author | Tseng, Wang-Dauh Jr | |
dc.contributor.author | Lin, Rung-Bin Jr | |
dc.date.accessioned | 2011-01-21T01:16:30Z | |
dc.date.accessioned | 2020-08-06T07:15:44Z | - |
dc.date.available | 2011-01-21T01:16:30Z | |
dc.date.available | 2020-08-06T07:15:44Z | - |
dc.date.issued | 2011-01-21T01:16:30Z | |
dc.date.submitted | 2010-12-16 | |
dc.identifier.uri | http://dspace.fcu.edu.tw/handle/2377/29930 | - |
dc.description.abstract | This paper presents a pattern run-length compression method. Compression is conducted by encoding 2|n| runs of compatible or inversely compatible patterns into codewords in both views either inside a single segment or across multiple segments. With the provision of high compression flexibility, this method can achieve significant compression. Experimental results for the large ISCAS’89 benchmark circuits have demonstrated that the proposed approach can achieve up to 67.64% of average compression ratio. | |
dc.description.sponsorship | National Cheng Kung University,Tainan | |
dc.format.extent | 6p. | |
dc.relation.ispartofseries | 2010 ICS會議 | |
dc.subject | automated test equipment (ATE) | |
dc.subject | pattern run-length | |
dc.subject | circuit under test (CUT) | |
dc.subject | test data compression | |
dc.subject.other | Computer Architecture, SoC, and Embedded Systems | |
dc.title | 2n Pattern Run-Length for Test Data Compression | |
分類: | 1995年 NCS 全國計算機會議 |
文件中的檔案:
檔案 | 描述 | 大小 | 格式 | |
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562_ICS2010.pdf | 283.47 kB | Adobe PDF | 檢視/開啟 |
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