Using Pipeline Architecture Technique for Implementing FPGA-Based Firewall

Abstract

This paper presents a pipeline architecture for Hardware Firewall packet classification implemented on FPGA. In this architecture the pipeline is a three layer MLP (Multi-Layer Perceptron). This architecture uses FPGA for implementation as it can be constructed only with few addition, subtraction and multiplication operations with high processing speed. The architecture classifies the packets from standard input TCP/IP packets based on rule sets tables. Experimental result shows the proposed architecture provides high accuracy with high speed of processing for hardware firewalls.