完整後設資料紀錄
DC 欄位語言
dc.contributor.authorSaeed, Ezzati
dc.contributor.authorHamid, Reza Naji
dc.contributor.authorAmir, Chegini
dc.date.accessioned2011-01-26T00:29:33Z
dc.date.accessioned2020-05-18T03:11:01Z-
dc.date.available2011-01-26T00:29:33Z
dc.date.available2020-05-18T03:11:01Z-
dc.date.issued2011-01-26T00:29:33Z
dc.date.submitted2011-01-10
dc.identifier.urihttp://dspace.lib.fcu.edu.tw/handle/2377/29941-
dc.description.abstractThis paper presents a pipeline architecture for Hardware Firewall packet classification implemented on FPGA. In this architecture the pipeline is a three layer MLP (Multi-Layer Perceptron). This architecture uses FPGA for implementation as it can be constructed only with few addition, subtraction and multiplication operations with high processing speed. The architecture classifies the packets from standard input TCP/IP packets based on rule sets tables. Experimental result shows the proposed architecture provides high accuracy with high speed of processing for hardware firewalls.
dc.description.sponsorshipNational Cheng Kung University,Tainan
dc.format.extent4p.
dc.relation.ispartofseries2010 ICS會議
dc.subject.otherComputer Architecture, SoC, and Embedded Systems
dc.titleUsing Pipeline Architecture Technique for Implementing FPGA-Based Firewall
分類:2010年 ICS 國際計算機會議(如需查看全文,請連結至IEEE Xplore網站)

文件中的檔案:
沒有與此文件相關的檔案。


在 DSpace 系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。