A VLSI Architecture for AES with CBC mode

Abstract

In the thesis, a pipelined architecture of AES plus CBC Encryption/Decryption IP (Intellectual Property) is proposed. This architecture implements the AES algorithm, the input data is a sequence of 128 bits and the cipher key is a sequence of 128, 192, or 256 bits. To provide the flexibility of interfacing with common microprocessors, the data bus width can be set to 8, 16, or 32 bits. To apply AES in a variety of applications, four “modes of operation” (ECB, CBC, CFB, and OFB) have been defined in the IP. To reduce the power consumption, the same set of Round Keys will not be generated many times for every data blocks because all of the Round Keys have been generated and stored in RAM by Key 2 Schedule. Obviously, it consumes less power to compute the same set of Round Keys. Compared with the widely used lookup-table architecture, the Euclid’s multiplicative inverse lookup-table architecture used in the thesis may reduce the hardware overhead of the S-box and InvS-box by an amount of 36.45%. The AES plus CBC Encryption/Decryption IP has been implemented and verified with both Xilnx Vertex 400 FPGA and TSMC 0.25 μm cell library. In the FPGA part, it operates at 30 MHz and can achieve a high throughput of 230.4 Mbps. It takes up LUTs of 73% and Block RAM of 80% in FPGA board. In the cell-based part, it operates at 156.25 MHz and can achieve a high throughput of 1200 Mbps. The core occupies the area of 1671.73 μm×1671.73 μm, which is approximately equivalent to 76610 gates, and consumes about 128.4 mW in the typical operating condition.