SOCs Test Scheduling using TAM Switch

Abstract

The progress of the SOC technologies has inspired the requirements of complex circuits. The potential complexity of SOCs results in the difficulty of testing and long testing time. The testing time of a SOC is determined by the total test bandwidth of TAM and the test sequence of cores. High bandwidth TAM provides faster test data access of cores and thus reduce the testing time of SOCs, but it also results in high area overhead. Besides, under the constraint of the total test bandwidth, the test sequence of cores affects the SOC testing time significantly. In this paper, we propose a TAM Switch based test scheduling algorithm for SOCs, under the constraint of fixed TAM width. Experimental results show the proposed approach obtains low testing time for all cases in SOC d695 and SOC p93791 benchmarks