題名: | Graph-based Wire Planning for Analog Circuits |
作者: | Lin, Cheng-Chiang Jr Wu, Pei-Shan Jr Yu, Jiun-Ying Jr Lin, Yu-Cheng Jr Huang, Hsin-Hsiung Jr Hsieh, Tsai-Ming Jr |
關鍵字: | Electro migration space reservation Wire Planning Obstacle-avoiding routing Graph theory |
期刊名/會議名稱: | NCS 2009 |
摘要: | In this paper, we propose the graph-based approach which constructs the electromigration-free wire planning according to the current characteristics of sources and sinks. The objective of this paper is to minimize the total wiring area of the wire planning without electromigration, i.e. enhance the mean time before failure. First, we construct the complete bipartite graph which the weight of each edge is with consideration of distance between each source-sink pair and current capacity for all sources and sinks. Second, we sort the weights of all edges with the ascending order. Third, the edge with the minimal current-distance weight is selected to remove from the complete bipartite graph. Furthermore, we iteratively update the supply current of the current source and the weights of the corresponding edges which are connected to the current source. Finally, the greedy method terminates until the current capacity of all sources are zero. Five benchmark circuits are used to evaluate the proposed algorithm and experimental results show that the proposed approach efficiently gets the better solution and effectively minimizes the wiring area with consideration of electromigration. |
日期: | 2011-03-24T23:39:26Z |
分類: | 2009年 NCS 全國計算機會議 |
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CEV 5-2.pdf | 500.18 kB | Adobe PDF | 檢視/開啟 |
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