Data Tunnel in DDRx Memory Controller

Abstract

With the growing imbalance between mul-ti-core and memory, the data access from memory system becomes one of the primary bottlenecks, particularly much data movement. To reduce the growing gap, tradi-tional approaches to reduce latency are mainly aimed at several factors such as the number of memory channels, the bandwidth of each channel, burst sizes, and scheduling requests dynamically, etc. For conventional DRAM, these approaches are reaching their practical limits. For in-stance, DMA popularly resolution still cannot eliminate this enormous gap due to the limited bus width and clock. This paper characterizes a performance examination of the DRAM-system architecture and the proposed memory controller can transfer data to destination and receive from source via data tunnel. In this design of data tunnel, while the lots of data are reading from source DRAM, the destination DRAM will capture data via data tunnel si-multaneously. The results of simulation experiments show that the data tunnel mechanism enhances the fifty four percentages periods of time.