應用於功率管理使用延遲可規劃之數位式電壓調節電路的設計與實現

Abstract

在電路設計時，並未考量產品在運算時會不斷的改變電壓且造成功率浪費，所以為了達到對外部電路消耗較低功率的期望，因此我們從這個方向開始了這次的專題計畫 本文章中主要分為三個部分，其中包含雙電壓源供應，與電壓比較機制，以及控制電壓源機制，我們將此雙電源設計在晶片上，依效能與功率消耗區分可為三段的調節模式：高電壓、低電壓與休眠，因為雙電源的設計，所以待測晶片上電壓供應的管理與分布會變更加的複雜。 比較電路藉由判斷外部電路產生的壓差在運作時，造成運算速度上的差別，再用DFF來進行分別，藉由判斷電路以及控制電路去控制電壓，改變電壓源開關，再回饋給外接電路，如此重複判斷外接電路在運作時所造成的電壓變化並且進行調變，進而修正至不影響運算輸出的穩定電壓。 傳統的DCDC技術是提供合適的供應電壓的一項裝置，偵測到電壓，再將電壓進行調整後，供應電壓給微處理器。其中有使用被動元件如電感和電容，因此，晶片中被動元件佔據大多數面積，除此之外，為了減少對電路的雜訊干擾，在大多數設計中，DCDC是獨立設計在電路的外部。此設計使用數位電路來調節電壓，除了可規劃的調整對電壓的靈敏度，自動化合成的電路設計，也可以很容易地結合其他電路做在單一顆晶片上，設計目標是動態控制晶片中各個子系統的電源電壓，在未來SoC 晶片裡需要具備有功率管理單元，將可使整個系統晶片達到低功率高效能的需求。

When the circuit was designed it was not considered that the product could continue to change the voltage and the resulting power would be wasted during the operation, so in order to meet the expectations of the external circuits low power consumption, so we started this project in this direction. The circuit is mainly divided into three parts in this article, which includes the dual voltage supply source, the voltage comparator, and the control voltage sources mechanism. We designed this chip with dual power, and it is according to performance and power consumption that it can be distinguished into three adjustment modes: high voltage, low voltage and sleep. Because it is a dual power supply design, the management and distribution of the test chip voltage supply becomes more complex. The comparator circuit generated in the external circuit t by determining the differential voltage during operation, causing a difference in speed of operation, and then comparing by DFF, and controlling the voltage and the voltage source switch by the judgment circuit and a control circuit, and then feeding it back to the external circuitry. Repeating the operation can determine the external circuit when the voltage variation caused and performs modulation, and then correction does not affect the operation to stabilize the output voltage. This design uses a digital circuit to regulate the voltage, in addition to adjusting the programming voltage sensitivity, and the automated synthesis circuit design can easily be combined with other circuits on a chip. The goal to control the various subsystems of the wafer voltage supply can be dynamically. The chip will enable the whole system to achieve low-power and high-performance. In the future, there is need to have a power management unit in the SOC chip.