A Superscalar Dual-Core Architecture for ARM ISA

Abstract

Recently, embedded systems increase the complexities of the applications and system designers must choose more powerful embedded processors to meet the complex applications. For keeping the system life time and saving the software reengineering cost, it is important for the designers of computer architectures to increase the performances of the instruction set architecture family. Consequently, this paper proposes a Superscalar Dual-Core (SDC) architecture consisting of two five-stage pipeline ARM processor cores and an instruction dispatched unit (which can fetch two instructions at once and dispatch the two instructions to both processor cores by proposed dispatched rules) to make the high instruction set compatibility and to support higher performance requirements. This paper presents the philosophy of the SDC architecture, and the structure of SDC programs. The paper also discusses performance issues in the SDC architecture, and compares it with the five-stage pipeline architecture. According to experimental results, the SDC architecture can obtain average 41% performance speedup comparing to the five-stage pipeline architecture.