Retargetable Exploration Methodology for Heterogeneous Multi-Core SOC

Abstract

We proposed an exploration methodology for the heterogeneous multi-core embedded System-On-Chip(SOC) design. Our key features are to define/implement an Target Architecture Description (TAD) language which can describe the target embedded microprocessors’ structural and instruction behaviors, automatically generate a retagetable instruction set simulator(ISS) which has multiple accurate, two-stages simulator acceleration functions, and establish a heterogeneous multi-core estimation framework which can plugin the heterogeneous simulators generated by our simulator generator. Instruction-set simulators are an important part of a today’s processor and software development. They are playing an important role within the architecture exploration, early system verification and pre-silicon software development. We can use the TAD to describe the ARM architecture. The compiled simulator which automatic generation is faster then the hand coded C simulator sixteen times, and the binary translate simulator is faster then the hand coded C simulator 27.2 times.