PIPD: Power Integrity Path Delay Analysis Tool

Abstract

IR-drop is a well-known signal integrity issue in very deep submicron technology. The voltage drop does not only induce circuit delay but also reduce the circuit noise margin from lower supply voltage and bring reliability issue from electromigration. PIPD is a gate level path delay analysis tool under insufficient current supplied condition. This tool could help designer fast compute/estimate the longest path delay when occurred voltage drop issues. In this paper, a maximum transition current computation tool is developed. Regard this research past works are pattern independent, which are worst-case predication. Due to the peak current overestimated from above researches, and the accurate peak current is dynamic behavior（pattern dependent）, so we use real functional test bench to activate gate transitions peak current. Our pattern dependent method is more realistic, the measurement results might lower and accurate than past works. Using PIPD could help design reasonable power rail, simulation results prove that our gate-level computation results are very closed to transistor-level simulation results by using HSPICE, the average differ ratios are less than 8%.