完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Shieh, Wann-Yun | |
dc.contributor.author | Hsu, Shu-Yi | |
dc.date.accessioned | 2009-08-23T04:43:18Z | |
dc.date.accessioned | 2020-05-25T06:52:04Z | - |
dc.date.available | 2009-08-23T04:43:18Z | |
dc.date.available | 2020-05-25T06:52:04Z | - |
dc.date.issued | 2007-01-25T06:49:06Z | |
dc.date.submitted | 2006-12-04 | |
dc.identifier.uri | http://dspace.lib.fcu.edu.tw/handle/2377/3466 | - |
dc.description.abstract | The multi-banked register file (MBRF) is one of the most effective approaches to resolve the complexity of the monolithic register files. In order to apply the multi-banked register file to a high-end embedded processor, we design the dynamic voltage (DVS) scaling approach for MBRF to satisfy the energy constraints. However, we found that distributed bank-access behavior prevents voltage scaling from identifying when a bank is active or not. To resolve this problem, in this paper, we analyze the access behavior of temporary-values, and change their storage in banks to increase the opportunities of power saving for infrequently-used register banks. We then turn these infrequently-used register banks into lower mode by our proposed DVS circuit. For a MBRF architecture with four banks, simulation results show that, on average, our approach reduces about 19% energy consumption while performance lose can be limitted by less than 2%, compared with the MBRF without DVS. | |
dc.description.sponsorship | 元智大學,中壢市 | |
dc.format.extent | 6p. | |
dc.format.extent | 3791945 bytes | |
dc.format.mimetype | application/pdf | |
dc.language.iso | zh_TW | |
dc.relation.ispartofseries | 2006 ICS會議 | |
dc.subject.other | Power-Aware Architecture Synthesis | |
dc.title | Power-Aware Register Assignment for Multi-Banked Register Files | |
分類: | 2006年 ICS 國際計算機會議 |
文件中的檔案:
檔案 | 描述 | 大小 | 格式 | |
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ce07ics002006000016.pdf | 3.7 MB | Adobe PDF | 檢視/開啟 |
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