Design of an Area-Efficient ASIC Architecture for Context-Based Binary Arithmetic Coding

Abstract

This paper presents a novel pipelined ASIC architecture for the context-based binary arithmetic encoder in JPEG2000, which is compatible with the arithmetic encoder defined in ISO/IEC 155444-1. By making use of a particularly 3-stage pipelined architecture, the proposed encoding architecture is able to process every input symbol within a single clock cycle. This architecture not only overcomes the problem of unfixed pipeline stages emerging from the uncertain times of renormalizations during the encoding phase, but also reduces the number of registers necessitated by the pipeline structure.