Pseudo-DCVSL Template for Power Awareness VLSI Circuit Design

Abstract

We design a pseudo-DCVSL dynamic logic by replacing the complemented network with a matched delay line rather than using the dual function of the target equation, whose low-power and small-in-area features are much better than the compared dual-rail DCVSL and dual-rail domino logics. Also, post-layout simulations are done to demonstrate all positive features and drawbacks of this circuit template; this template provides flexible techniques for low power design with stable performance. Besides, the layout area of the pseudo-DCVSL is always smaller than the compared logic families; for instance, the matched delay circuitry is much smaller than the complemented network in the dual-rail structure in general. 10 single-level logic equations from SIS library were selected and the test result shows more than 20% area reduction and 26% less power consumption in average. Furthermore, we simulate multi-level high fan-in AND gate and obtain remarkable result on both the area and power efficiency.