Analysis of Iterative and Simulated Annealing HW/SW Co-Synthesis Algorithms for Energy-Aware Network-on-Chip Design

Abstract

Network-on-Chip (NoC) has been proposed to overcome the complex on-chip communication problem of SoC (System-on-Chip) design in deep submicron. A complete NoC design contains exploration on both hardware and software architectures. The hardware architecture includes the selection of PEs (Processing Elements) with multiple types and their topology. The software architecture contains the allocation of tasks to PEs, scheduling of tasks and their communications. To find the best hardware design for the target tasks, both hardware and software architectures need to be considered simultaneously. There are two broad categories of HW/SW co-synthesis algorithms for NoC design: iterative algorithms and simulated-annealing (SA) algorithms. In this paper, we study the two categories of co-synthesis algorithms and revise them for energy-aware NoC design. Both performance and solution quality of the two categories of co-synthesis algorithms are analyzed in this paper.