Reduction of Test Power during Test Application in Full-Scan Sequential Circuits with Multiple Capture Techniques

Abstract

In this paper, we propose a multiple capture approach to reduce the peak power as well as average power consumption during testing. The basic idea of the proposed approach is to divide a scan chain into a number of sub-scan chains, and only one sub-scan chain will be enabled at a time during the scan shift or capture operations. To efficiently deal with the “capture violation problem”, we develop a test pattern insertion method to solve this problem. To reduce the number of patterns to be inserted, a scan chain partition method by exploiting don’t care responses and a test pattern ordering method are also developed. The proposed approach can be easily implemented for any large full-scan sequential circuits. Experimental results for large ISCAS’89 benchmark circuits show that our approach can reduce the peak power and average power dissipation during testing significantly.