題名 | 作者 | 日期 |
A Method of Improving Translating Performance in the CISC/RISC Hybrids | Jian, Wen-Bin; Chen, Chang-Jiu | 2006-10-30T01:39:54Z |
A Novel TLB Architecture to Reduce the Miss Rate in Context Switching | Chen, Chang-Jiu; Cheng, Wei-Min; Chang, Chi-Wen; Liao, Wen-Chiuan | 2006-10-18T07:50:53Z |
An Asynchronous Processor Simulator | Lee, Tse-Hao; Chen, Chang-Jiu | 2006-10-13T02:37:28Z |
An Improved Dispatch and Issue Mechanis with Dynamic Instruction Reuse | Chen, Yi-Ming; Chen, Chang-Jiu | 2006-10-30T01:20:39Z |
Branch Direction Prediction With Vote Predictor | Lin, Hung-Ching; Chen, Chang-Jiu | 2006-10-27T03:19:53Z |
Construct QoS End-to-end Virtual Path With Lagrangean Relaxation Method | Chen, Chang-Jiu; Liu, Ming-Su | 2006-10-18T07:45:40Z |
Improvement for Reducing Latency of Load Instructions | Liu, Wen-Jun; Chen, Chang-Jiu | 2006-10-30T01:17:25Z |
Improving Branch Target Prediction with Register References | Liu, Yueh-Hung; Chen, Chang-Jiu | 2006-10-18T08:27:15Z |
Instruction Decoder Implemented with Balsa for an Asynchronous Pipelined 8051 compatible Microcontroller | Chen, Chang-Jiu; Cheng, Wei-Min; Wang, Tuan-Chieh; Chang, Yuan-Teng; Tsai, Hung-Yue | 2009-02-09T02:41:56Z |
TFT-LCD Timing Control Based on FPGA | Chen, Chang-Jiu; Peng, Bing-Chia | 2007-01-26T01:30:22Z |
The Design of Asynchronous Processor | Chen, Chang-Jiu; Shiu, Chih-Chiang; Wu, Men-Shu | 2006-10-16T01:50:27Z |