瀏覽 的方式: 作者 Chen, Tien-Fu
顯示 1 到 4 筆資料,總共 4 筆
題名 | 作者 | 日期 |
A 500MHz, 8-Stage Pipeline RISC Microprocessor Design with Sub-Computing | Hu, Ya-Lun; Chang, Ming-Ku; Chen, Tien-Fu; Shiu, Fang-Yu; Cheng, You-Hsiang | 2007-01-25T06:12:32Z |
Adaptively Speculative Execution for Wide-Issue Superscalar Processors | Lin, Chia-Chang; Chen, Tien-Fu | 2006-10-27T03:13:28Z |
Retargetable Exploration Methodology for Heterogeneous Multi-Core SOC | Wen, Che-Neng; Chen, Tien-Fu | 2007-01-25T06:15:38Z |
Simultaneous Multithreading RISC Processor with Non-blocking Load/Store | Chen, Hao-Sheng; Shiu, Fang-Yu; Chan, Yi-Chao; Chen, Tien-Fu | 2007-01-25T06:17:31Z |