瀏覽 的方式： 作者 Tseng, Yih-Long
顯示 1 到 3 筆資料，總共 3 筆
| 題名 | 作者 | 日期 |
|---|---|---|
| An FIFO Memory Design for 8-to-32 Data Exchange Bus | Wang, Chua-Chin; Tseng, Yih-Long; Chen, Yi-Wei | 2006-10-18T10:55:18Z |
| Robust Reference Clock Generator Design for DDR Synchronous Devices | Wang, Chua-Chin; Tseng, Yih-Long; Chen, Chi-Wen | 2006-10-13T09:37:14Z |
| Robust Reference Clock Generator Design for DDR Synchronous Devices | Wang, Chua-Chin; Tseng, Yih-Long; Chen, Chi-Wen | 2006-10-18T10:56:21Z |