Low-cost Two's Complement Multipliers Using Signed Binary Digits for High-speed Digital Systems

Abstract

Multiplication is the most important operation in many high-speed digital systems. Redundant binary number system has been used to design fast multipliers, but whose area is probably larger than other kind of multipliers. In this paper, area-efficient two’s complement multipliers using binary signed-digit number system are designed for digital systems with constant data size by truncating the 2n-bit product into n-bit. Based on the variable correction value scheme, a novel carry compensation formulation and corresponding circuit are developed to largely degrade the product error. Simulation results show that the proposed truncated multipliers are more accurate than other truncated architectures while maintaining high speed and small area. When applying to discrete cosine transform (DCT), the proposed multiplier can significantly reduce the area and power of DCT circuit and still obtain good image quality.