完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | 伍朝欽 | |
dc.date.accessioned | 2009-06-02T08:38:29Z | |
dc.date.accessioned | 2020-07-05T06:34:15Z | - |
dc.date.available | 2009-06-02T08:38:29Z | |
dc.date.available | 2020-07-05T06:34:15Z | - |
dc.date.issued | 2006-06-15T03:20:01Z | |
dc.date.submitted | 2003-12-19 | |
dc.identifier.uri | http://dspace.fcu.edu.tw/handle/2376/1950 | - |
dc.description.abstract | Previous research show that, chip-multiprocessors have better speedup for floating-point-operation-intensive benchmark programs but worse for integer- operation-intensive application programs when compared with superscalar architectures. In this paper, we propose a novel microprocessor, combining the advantages of superscalar and chip-multiprocessor architectures, to provide the best performance regardless of workload types. Our architecture has two execution modes: one for multithreads and one for single thread. The new CPU can issue and execute sixteen instructions during each cycle regardless of the execution mode. In the first mode, the system behaves like a conventional chip-multiprocessor. On the other hand, we integrated separate four processing elements into a single logical superscalar processor in the second mode. When executing a program, the architecture keeps switching between two execution modes according to the feature of the subsequent codes to be run. | |
dc.description.sponsorship | 逢甲大學,台中市 | |
dc.format.extent | 8P. | |
dc.format.extent | 303608 bytes | |
dc.format.mimetype | application/pdf | |
dc.language.iso | zh_TW | |
dc.relation.ispartofseries | 中華民國92年全國計算機會議 | |
dc.subject | Chip-Multiprocessor | |
dc.subject | Superscalar Processor | |
dc.subject | Multithreaded Architecture | |
dc.subject | Speculative Execution | |
dc.subject | Instruction-Level Parallelism. | |
dc.subject.other | 其他領域 | |
dc.title | 具雙重執行模式之單晶片多處理機架構 | |
分類: | 2003年 NCS 全國計算機會議 |
文件中的檔案:
檔案 | 描述 | 大小 | 格式 | |
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OT_1382003256.pdf | 296.49 kB | Adobe PDF | 檢視/開啟 |
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