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dc.contributor.author伍朝欽
dc.date.accessioned2009-06-02T08:38:29Z
dc.date.accessioned2020-07-05T06:34:15Z-
dc.date.available2009-06-02T08:38:29Z
dc.date.available2020-07-05T06:34:15Z-
dc.date.issued2006-06-15T03:20:01Z
dc.date.submitted2003-12-19
dc.identifier.urihttp://dspace.fcu.edu.tw/handle/2376/1950-
dc.description.abstractPrevious research show that, chip-multiprocessors have better speedup for floating-point-operation-intensive benchmark programs but worse for integer- operation-intensive application programs when compared with superscalar architectures. In this paper, we propose a novel microprocessor, combining the advantages of superscalar and chip-multiprocessor architectures, to provide the best performance regardless of workload types. Our architecture has two execution modes: one for multithreads and one for single thread. The new CPU can issue and execute sixteen instructions during each cycle regardless of the execution mode. In the first mode, the system behaves like a conventional chip-multiprocessor. On the other hand, we integrated separate four processing elements into a single logical superscalar processor in the second mode. When executing a program, the architecture keeps switching between two execution modes according to the feature of the subsequent codes to be run.
dc.description.sponsorship逢甲大學,台中市
dc.format.extent8P.
dc.format.extent303608 bytes
dc.format.mimetypeapplication/pdf
dc.language.isozh_TW
dc.relation.ispartofseries中華民國92年全國計算機會議
dc.subjectChip-Multiprocessor
dc.subjectSuperscalar Processor
dc.subjectMultithreaded Architecture
dc.subjectSpeculative Execution
dc.subjectInstruction-Level Parallelism.
dc.subject.other其他領域
dc.title具雙重執行模式之單晶片多處理機架構
分類:2003年 NCS 全國計算機會議

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