完整後設資料紀錄
DC 欄位 | 值 | 語言 |
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dc.contributor.author | Musleh, Maan | |
dc.contributor.author | Aboelaze, Mokhtar | |
dc.date.accessioned | 2009-06-02T07:05:18Z | |
dc.date.accessioned | 2020-05-25T06:48:20Z | - |
dc.date.available | 2009-06-02T07:05:18Z | |
dc.date.available | 2020-05-25T06:48:20Z | - |
dc.date.issued | 2009-01-19T06:55:42Z | |
dc.date.submitted | 2009-01-19 | |
dc.identifier.uri | http://dspace.lib.fcu.edu.tw/handle/2377/11091 | - |
dc.description.abstract | Discrete Fourier Transform is one of the most important operations in digital signal processing. DFT is used in many applications in communication systems and digital signal processing. DFT is also used in UWB OFDM and in IEEE802.11n. Energy consumption in portable and wireless devices is a crucial factor in the design of such sys- tems. In this paper, we propose an FFT processor based on the famous pipelined FFT architecture. Our design does not require any RAM and replaces it with bu ers. Our de- sign is based on 2-D FFT and does not require the power hungry RAM, instead the RAM is replaced by delay lines and a simple circuit to con gure the delay lines. Our design consumes less energy compared with processors with RAM, and can handle any size FFT (not only squared size). Index Terms|Fast Fourier Transform, Modular FFT ar- chitecture, Pipelined FFT, Low power | |
dc.description.sponsorship | 淡江大學,台北縣 | |
dc.format.extent | 6p. | |
dc.relation.ispartofseries | 2008 ICS會議 | |
dc.subject.other | Computer Architecture | |
dc.title | Enhanced RAM-less Modular 2-Dimensional Pipelined FFT | |
分類: | 2008年 ICS 國際計算機會議 |
文件中的檔案:
檔案 | 描述 | 大小 | 格式 | |
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ce07ics002008000044.pdf | 322.3 kB | Adobe PDF | 檢視/開啟 |
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