完整後設資料紀錄
DC 欄位語言
dc.contributor.authorMusleh, Maan
dc.contributor.authorAboelaze, Mokhtar
dc.date.accessioned2009-06-02T07:05:18Z
dc.date.accessioned2020-05-25T06:48:20Z-
dc.date.available2009-06-02T07:05:18Z
dc.date.available2020-05-25T06:48:20Z-
dc.date.issued2009-01-19T06:55:42Z
dc.date.submitted2009-01-19
dc.identifier.urihttp://dspace.lib.fcu.edu.tw/handle/2377/11091-
dc.description.abstractDiscrete Fourier Transform is one of the most important operations in digital signal processing. DFT is used in many applications in communication systems and digital signal processing. DFT is also used in UWB OFDM and in IEEE802.11n. Energy consumption in portable and wireless devices is a crucial factor in the design of such sys- tems. In this paper, we propose an FFT processor based on the famous pipelined FFT architecture. Our design does not require any RAM and replaces it with bu ers. Our de- sign is based on 2-D FFT and does not require the power hungry RAM, instead the RAM is replaced by delay lines and a simple circuit to con gure the delay lines. Our design consumes less energy compared with processors with RAM, and can handle any size FFT (not only squared size). Index Terms|Fast Fourier Transform, Modular FFT ar- chitecture, Pipelined FFT, Low power
dc.description.sponsorship淡江大學,台北縣
dc.format.extent6p.
dc.relation.ispartofseries2008 ICS會議
dc.subject.otherComputer Architecture
dc.titleEnhanced RAM-less Modular 2-Dimensional Pipelined FFT
分類:2008年 ICS 國際計算機會議

文件中的檔案:
檔案 描述 大小格式 
ce07ics002008000044.pdf322.3 kBAdobe PDF檢視/開啟


在 DSpace 系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。