A Optimal Arbiter Design for NoC

Abstract

A new fast centralized arbiter, which is a modular design and easy for hardware implementation, is proposed. We had derived the state diagram of the arbiter as well as its truth tables and Karnaugh maps, and had designed a set of optimal Boolean functions and the corresponding circuit for the arbiter. This new arbiter is fair for any input combinations and faster than all previous arbiters we knew. Using Synopsys design tools with TSMC 0.18μm technology, the design results have shown that our arbiter has 22.8% improvement of execution time and 39.1% of cost (area) reduction compared with the existing fastest arbiter, SA [7]. Because of this small arbiter’s the high-performance, it is extremely useful for the realizations of NoC routers, MPSoC arbitration, and ultra-high-speed switches. This new arbiter is being applied for a patent of the ROC (application No.: 0971xxxxx).