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dc.contributor.authorLee, Tse-Hao
dc.contributor.authorChen, Chang-Jiu
dc.date.accessioned2009-08-23T04:46:46Z
dc.date.accessioned2020-05-29T06:18:46Z-
dc.date.available2009-08-23T04:46:46Z
dc.date.available2020-05-29T06:18:46Z-
dc.date.issued2006-10-13T02:37:28Z
dc.date.submitted2001-12-20
dc.identifier.urihttp://dspace.fcu.edu.tw/handle/2377/1129-
dc.description.abstractAsynchronous processors have become a new direction of modern architecture research these years. To compare the improvement of different approaches without designing a real chip, we need a code-based simulator. The SimAsync, an asynchronous processor simulator was developed. The simulator tools are based on SimpleScalar[1], a public simulator of modern microprocessors. out that some problems, like branch miss penalty and data dependency, cannot be solved easily in asynchronous environment. The power dissipation reduction is not as good as expected, neither. Because the additional control logics between each stage also need power, the implementation of control logic should be more refined. On the other hand,
dc.description.sponsorship中國文化大學,台北市
dc.format.extent12p.
dc.format.extent1301577 bytes
dc.format.mimetypeapplication/pdf
dc.language.isozh_TW
dc.relation.ispartofseries2001 NCS會議
dc.subjectSimAsync
dc.subjectSimpleScalar
dc.subjectsimulator
dc.subjectasynchronous
dc.subject.otherAdvanced Microarchitecture
dc.titleAn Asynchronous Processor Simulator
分類:2001年 NCS 全國計算機會議

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