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dc.contributor.authorHsiung, Pao-Ann
dc.contributor.authorCheng, Shu-Yu
dc.date.accessioned2009-08-23T04:41:33Z
dc.date.accessioned2020-05-25T06:39:26Z-
dc.date.available2009-08-23T04:41:33Z
dc.date.available2020-05-25T06:39:26Z-
dc.date.issued2006-10-13T08:13:20Z
dc.date.submitted2002-12-18
dc.identifier.urihttp://dspace.lib.fcu.edu.tw/handle/2377/1198-
dc.description.abstractMost verification tools and methodologies such as model checking, equivalence checking, hardware verification, software verification, and hardware-software coverification often flatten out the behavior of a target system before verification. Inherent modularities, either explicit or implicit, functional or structural, are not exploited by these tools and algorithms. In this work, we show how assume-guarantee reasoning (AGR) can be used for such exploitations by integrating AGR into a verification tool. Targeting at real-time embedded systems, we propose procedures to automatically generate assumptions, guarantees, and time constraints, which otherwise require manual efforts and human creativity. Through a complex but comprehensible realtime embedded system example such as a Vehicle Parking Management System (VPMS), we illustrate the feasibility of the AGR approach and the extremely large (as much as 96%) reduction possible in state-space sizes when AGR is applied. Due to AGR, we also found five errors in the VPMS design using much lesser CPU time and memory space than possible without AGR.
dc.description.sponsorship東華大學,花蓮縣
dc.format.extent20p.
dc.format.extent149767 bytes
dc.format.mimetypeapplication/pdf
dc.language.isozh_TW
dc.relation.ispartofseries2002 ICS會議
dc.subjectassume-guarantee reasoning
dc.subjectmodular verification
dc.subjectmodel-checking
dc.subjectstate-space reduction techniques
dc.subjectreal-time embedded systems
dc.titleAutomating Formal Modular Verification of Asynchronous Real-Time Embedded Systems
分類:2002年 ICS 國際計算機會議

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