Efficient low-complexity architectures for computing exponentiation

Abstract

In this investigation, we present cellular architecture for performing AB2 multiplication in a class field GF(2m), where the definition by an irreducible polynomial for the field is an all-one polynomial (AOP). This multiplier is highly regular, modular, and thus suited to VLSI implementation. For finite field multiplication and exponentiation, we conclude that our proposed is more efficient as their basic cells have less computation time and circuit low-complexity. Furthermore, comparing the related cellular architecture reveal that our constructed multipliers are shorter than the conventional multipliers for per cell circuit complexity and computing delay time. In addition, based on pipeline architectures, we also produced to compute exponentiation.