題名: | A Novel Strategy for Pipelining Restricted Vector Clocks in Distributed Systems |
作者: | Lin, Hwa-Chuan Lee, SingLing |
關鍵字: | Clock overflow distributed systems timestamp vector clocks |
期刊名/會議名稱: | 2002 ICS會議 |
摘要: | The vector clocks (VC) mechanism has been employed to solve a wide variety of problems in many applications, provided that the bit size of each component in the VC is always suÆcient. However, this may lead to an extremely large overhead in communication bandwidth and storage as the number of processes gets to be very large. Otherwise, the VC resetting procedures must be deployed and invoked carefully, which results in a restricted vector clock (RVC) property. The PVC employs two dierent representations to denote the meanings of VC in dierent cycles, so that the monotonic characteristic of VC is maintained for the execution of any applications. |
日期: | 2006-10-16T03:42:34Z |
分類: | 2002年 ICS 國際計算機會議 |
文件中的檔案:
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ce07ics002002000045.PDF | 279.39 kB | Adobe PDF | 檢視/開啟 |
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