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dc.contributor.authorDeng, Yan-Xiang
dc.contributor.authorChang, Yu-Ching
dc.contributor.authorHwang, Chao-Jang
dc.date.accessioned2009-06-02T06:39:45Z
dc.date.accessioned2020-05-25T06:41:26Z-
dc.date.available2009-06-02T06:39:45Z
dc.date.available2020-05-25T06:41:26Z-
dc.date.issued2006-10-16T05:57:19Z
dc.date.submitted2004-11-15
dc.identifier.urihttp://dspace.lib.fcu.edu.tw/handle/2377/1594-
dc.description.abstractWith the advance of science and technology, information products be required with light and thin, hence how to design a system into a single chip become a trend, the embedded system is typical example. Today the specification of products are changeful and various. How to lengthen the product lifetime on the market and to obtain more profits becomes an important issue. Our paper proposes a partial reconfigurable architecture of embedded system, the system combine one major MPU (MicroProcessor Unit) and many reconfigurable function units. Utilize the characteristic of FPGA (Field Programmable Gate Array), we could reconfigure the function units according to demand for specific function and change the architecture of hardware to satisfy different kinds of application. In addition, it can also promote computing efficiency by hardware circuit. Therefore, this architecture probably becomes an optimized system between ASIC (Application Specific Integrated Circuit) and GPP (General-Purpose Processor).
dc.description.sponsorship大同大學,台北市
dc.format.extent4p.
dc.format.extent450654 bytes
dc.format.mimetypeapplication/pdf
dc.language.isozh_TW
dc.relation.ispartofseries2004 ICS會議
dc.subjectFPGA
dc.subjectPartial Reconfigurable
dc.subjectEmbedded System
dc.subject.otherMiscellaneous
dc.titleUsing FPGA to Implement a Partial Reconfigurable Architecture of Embedded System
分類:2004年 ICS 國際計算機會議

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