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dc.contributor.authorChen, Shih-Lun
dc.contributor.authorJou, Jer-Min
dc.contributor.authorSun, Chien-Ming
dc.contributor.authorWu, Yuan-Chin
dc.contributor.authorYang, Haoi
dc.contributor.authorSu, Hong-Yi
dc.date.accessioned2009-06-02T06:37:31Z
dc.date.accessioned2020-05-25T06:43:37Z-
dc.date.available2009-06-02T06:37:31Z
dc.date.available2020-05-25T06:43:37Z-
dc.date.issued2006-10-16T05:57:31Z
dc.date.submitted2004-12-15
dc.identifier.urihttp://dspace.lib.fcu.edu.tw/handle/2377/1596-
dc.description.abstractToday, the cost of mask in SoC is increasing rapidly. Designing a complex system-ona- chip (SoC) confronts many challenges. Networkson- a-chip (NoC) is a new architectural template, which helps to meet many of these challenges and enables fast time to market for new designs. How to transfer high-speed and macro data for computing and reusing macro transistors proves to be more and more important in the area of IC design. The reconfigurable processor turns into a research focus by many SoC researchers in the world. This paper offers a new powerful, flexible, and reusable reconfigurable processor for NoC, which will process no matter general or special purpose applications with high performance. It could handle software well like a superscalar CPU and process some special applications with macro data efficiently like an ASIC. Our results show that the reconfigurable processor design greatly improves the performance than traditional processor design.
dc.description.sponsorship大同大學,台北市
dc.format.extent6p.
dc.format.extent409824 bytes
dc.format.mimetypeapplication/pdf
dc.language.isozh_TW
dc.relation.ispartofseries2004 ICS會議
dc.subjectReconfigurable
dc.subjectNoC
dc.subject.otherMiscellaneous
dc.titleReconfigurable Processor Core Design for Network-on-a-Chip
分類:2004年 ICS 國際計算機會議

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